Reconfigurable computing for digital signal processing

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore’s Law, and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.

Three goals have driven the development of DSP implementations:
1. Data parallelism
2. Application-specific specialization
3. Functional flexibility.

In general, design decisions regarding DSP system implementation require tradeoffs between these three system goals. As a result, a wide variety of specialized hardware implementations and associated design tools have been developed for DSP including associative processing, bit-serial processing, online arithmetic, and systolic processing. As implementation technologies have become available, these basic approaches have matured to meet the needs of application designers.

As shown in the Table, various cost metrics have been developed to compare the quality of different DSP implementations. Performance has frequently been the most critical system requirement since DSP systems often have demanding real-time constraints. In the past two decades, however, the cost has become more significant as DSP has migrated from predominantly military and scientific applications into numerous low-cost consumer applications. Over the past ten years, energy consumption has become an important measure as DSP techniques have been widely applied in portable, battery-operated systems such as cell phones, CD players, and laptops. Finally, flexibility has emerged as one of the key differentiators in DSP implementations since it allows changes to system functionality at various points in the design life cycle. The results of these cost tradeoffs have resulted in four primary implementation options including application-specific integrated circuits (ASICs), programmable digital signal processors (PDSPs), general-purpose microprocessors, and reconfigurable hardware. Each implementation option presents different trade-offs in terms of performance, cost, power and flexibility.

An important aspect of reconfigurable devices is the ability to reconfigure functionality in response to changing operating conditions and application data sets. While SRAM-based FPGAs have supported slow millisecond reconfiguration rates for some time, only recently have devices been created that allow for rapid device reconfiguration at run-time. Dynamically reconfigurable FPGAs, or DPGAs, contain multiple interconnect and logic configurations for each programmable location in a reconfigurable device. Often these architectures are designed to allow configuration switching in a small number of system clock cycles measuring nanoseconds rather than milliseconds. While several DPGA devices have been developed in research environments, none are currently commercially available due to the large overhead costs associated with the required large configuration memory. To promote reconfiguration at lower hardware cost, several commercial FPGA families have been introduced that allow for fast, partial reconfiguration of FPGA functionality from off-chip memory resources. A significant challenge to the use of these reconfigurables is the development of compilation software that will partition and schedule the order in which computation will take place and will determine which circuitry must be changed. While some preliminary work in this area has been completed, more advanced tools are needed to fully leverage the new hardware technology. Other software approaches that have been applied to dynamic reconfiguration include the definition of hardware subroutines and the dynamic reconfiguration of instruction sets.

Burleson, Wayne. “Reconfigurable Computing for Digital Signal Processing: A Survey.” The Journal of VLSI Signal Processing, 2001.

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